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July 2005 rev 0.2 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Features
Output frequency range: 25 MHz to 200 MHz Input frequency range: 25 MHz to 200 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 2.5% max Output duty cycle variation Nine Clock outputs: Drive up to 18 clock lines Two reference clock inputs: LVPECL or LVCMOS 150-ps max output-output skew Phase-locked loop (PLL) bypass mode `SpreadTrak' Output enable/disable Pin-compatible with MPC9351 and CY29351. Industrial temperature range: -40C to +85C 32-pin 1.0mm TQFP & LQFP Package.
ASM5I9351
The ASM5I9351 features LVPECL and LVCMOS reference clock inputs and provides 9 outputs partitioned in 4 banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table.2. These dividers allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS compatible output can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see the Table 1. When PLL_EN is LOW, PLL is bypassed and the reference
Functional Description
The ASM5I9351 is a low voltage high performance
clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.
200MHz PLL-based zero delay buffer designed for high speed clock distribution applications.
Alliance Semiconductor 2575, Augustine Drive * Santa Clara, CA * Tel: 408.855.4900 * Fax: 408.855.4999 * www.alsc.com
Notice: The information in this document is subject to change without notice.
July 2005 rev 0.2
Block Diagram SELA PLL_EN REF_SEL TCLK PECL_CLK
ASM5I9351
Phase Detector
VCO 200-500MHz LPF
+2/ +4
QA
FB_IN
+4/ +8
QB QC0 QC1 QD0 QD1 QD2 QD3 QD4
SELB
+4/ +8
SELC
+4/ +8
OE# SELD
REF_SEL
VDDQB
TCLK
Pin Configuration
PLL_EN
VSS
QA
32 31 30 29 28 27 26 25 AVDD FB_IN SELA SELB SELC SELD AVSS PECL_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 QC0 VDDQC QC1 VSS QD0 VDDQD QD1 VSS
ASM5I9351
VSS 21 20 19 18 17 QD2
VDD
PECL_CLK#
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
VDDQD
VSS
OE#
QD4
QD3
QB
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Pin Configuration1 Pin # Pin Name
8 9 30 28 26 22, 24 12, 14, 16, 18, 20 2 10 31 32 3, 4, 5, 6 27 23 15, 19 1 11 7 13, 17, 21, 25, 29 PECL_CLK PECL_CLK# TCLK QA QB QC(1:0) QD(4:0) FB_IN OE# PLL_EN REF_SEL SEL(A:D) VDDQB VDDQC VDDQD AVDD VDD AVSS VSS
ASM5I9351
I/O
I, PU I, PU/PD I, PD O O O O I, PD I, PD I, PU I, PD I, PD Supply Supply Supply Supply Supply Supply Supply
Type
Analog Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD VDD VDD Ground Ground
Description
LVPECL reference clock input. LVPECL reference clock input. Weak pull-up to VDD/2. LVCMOS/LVTTL reference clock input Clock output bank A Clock output bank B Clock output bank C Clock output bank D Feedback clock input. Connect to an output for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. Output enable/disable input. See Table 2. PLL enable/disable input. See Table 2. Reference select input. See Table 2. Frequency select input, Bank (A:D). See Table 2. 2.5V or 3.3V Power supply for bank B output clock2,3 2.5V or 3.3V Power supply for bank C output clocks2,3 2.5V or 3.3V Power supply for bank D output clocks2,3 2.5V or 3.3V Power supply for PLL2,3 2.5V or 3.3V Power supply for core, inputs, and bank A output clock2,3 Analog ground Common ground
Note: 1 PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output power supply pins.
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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Table 1: Frequency Table Feedback Output Divider
/2 /4 /8
ASM5I9351
VCO
Input Clock * 2 Input Clock * 4 Input Clock * 8
Input Frequency Range (AVDD = 3.3V)
100 MHz to 200 MHz 50 MHz to 125 MHz 25 MHz to 62.5 MHz
Input Frequency Range (AVDD = 2.5V)
100 MHz to 190MHz 50 MHz to 95MHz 25 MHz to 47.5MHz
Table 2: Function Table Control
REF_SEL PLL_EN OE# SELA SELB SELC SELD
Default
0 1 0 0 0 0 0
0
PCLK Bypass mode, PLL disabled. The input clock connects to the output dividers Outputs enabled /2 (Bank A) /4 (Bank B) /4 (Bank C) /4 (Bank D)
1
TCLK PLL enabled. The VCO output connects to the output dividers Outputs disabled (three-state), VCO running at its minimum frequency / 4 (Bank A) / 8 (Bank B) / 8 (Bank C) / 8 (Bank D)
Absolute Maximum Ratings Parameter
VDD VDD VIN VOUT VTT LU RPS TS TA TJ OJC OJA ESDH FIT
Description
DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch Up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time
Condition
Functional Relative to VSS Relative to VSS Functional Ripple Frequency < 100 kHz Non-functional Functional Functional Functional Functional
Min
-0.3 2.375 -0.3 -0.3 200
Max
5.5 3.465 VDD+ 0.3 VDD+ 0.3 VDD /2 150
Unit
V V V V V mA mVp-p C C C C/W C/W Volts ppm
-65 -40 42 105 2000 10
+150 +85 +150
Manufacturing test
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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DC Electrical Specifications (VDD = 2.5V 5%, TA = -40C to +85C) Parameter
VIL VIH VPP VCMR VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT
ASM5I9351
Description
Input Voltage, Low Input Voltage, High Peak-Peak Input Voltage Common Mode Range1 Output Voltage, Low Input Current, Low3 Input Current, High3 PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance
2 2
Condition
LVCMOS LVCMOS LVPECL LVPECL IOL= 15mA IOH= -15mA VIL= VSS VIL= VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz Outputs loaded @ 200 MHz
Min
1.7 250 1.0 1.8 14
Typ
5 180 210 4 18
Max
0.7 VDD+0.3 1000 VDD- 0.6 0.6 -100 100 10 7 22
Unit
V V mV V V V A A mA mA mA pF
Output Voltage, High
Note: 1 VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 2.Driving one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 series terminated transmission lines. 3.Inputs have pull-up or pull-down resistors that affect the input current.
DC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C) Parameter
VIL VIH VPP VCMR VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT
Description
Input Voltage, Low Input Voltage, High Peak-Peak Input Voltage Common Mode Range1 Output Voltage, Low2 Output Voltage, High2 Input Current, Low3 Input Current, High3 PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance
Condition
LVCMOS LVCMOS LVPECL LVPECL IOL= 24 mA IOL= 12 mA IOH= -24 mA VIL= VSS VIL= VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz Outputs loaded @ 200 MHz
Min
2.0 250 1.0 2.4 12
Typ
5 270 300 4 15
Max
0.8 VDD+0.3 1000 VDD- 0.6 0.55 0.30 -100 100 10 7 18
Unit
V V mV V V V A A mA mA mA pF
Note: 1 VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 2.Driving one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 series terminated transmission lines. 3.Inputs have pull-up or pull-down resistors that affect the input current.
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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AC Electrical Specifications (VDD = 2.5V 5%, TA = -40C to +85C) 1 Parameter
fVCO
ASM5I9351
Description
VCO Frequency
Condition
/2 Feedback
Min
200 100 50 25 0 25 500 1.2 100 50 25 47.5 45 0.1 -100 -100 -
Typ
2.2 0.85 0.6 175 -
Max
380 190 95 47.5 200 75 1000 VDD- 0.6 1.0 190 95 47.5 52.5 55 1.0 100 100 150 10 10 150 250 100 175 1
Unit
MHz
fin
Input Frequency
/4 Feedback /8 Feedback Bypass mode (PLL_EN = 0)
MHz
frefDC VPP VCMR tr, tf fMAX
Input Duty Cycle Peak-Peak Input Voltage Common Mode Range2 TCLK Input Rise/FallTime Maximum Output Frequency LVPECL LVPECL 0.7V to 1.7V /2 Output /4 Output /8 Output fMAX < 100 MHz fMAX > 100 MHz 0.6V to 1.8V TCLK to FB_IN PCLK to FB_IN
% mV V nS MHz
DC tr, tf t() tsk(O) tPLZ, HZ tPZL, ZH BW
Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3dB) Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time
% nS pS pS nS nS MHz
/2 Feedback /4 Feedback /8 Feedback Same frequency Multiple frequencies Same frequency Multiple frequencies
-
tJIT(CC) tJIT(PER) tJIT() tLOCK
pS pS pS mS
Note: 1 AC characteristics apply for parallel output termination of 50 to VTT. Parameters are guaranteed by characterization and are not 100% tested. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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July 2005 rev 0.2
AC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C)1 Parameter
fVCO
ASM5I9351
Description
VCO Frequency
Condition
/2 Feedback /4 Feedback
Min
200 100 50 25 0 25
Typ
2.2 0.85 0.6 175 -
Max
500 200 125 62.5 200 75 1000 VDD- 0.9 1.0 200 125 62.5 52.5 55 1.0 100 100 150 350 10 10 150 250 100 150 1
Unit
MHz
fin
Input Frequency
/8 Feedback Bypass mode (PLL_EN = 0) LVPECL LVPECL 0.8V to 2.0V /2 Output /4 Output /8 Output fMAX < 100 MHz fMAX > 100 MHz 0.8V to 2.4V TCLK to FB_IN, same VDD PCLK to FB_IN, same VDD Banks at same voltage Banks at different voltages
MHz
frefDC VPP VCMR tr, tf fMAX
Input Duty Cycle Peak-Peak Input Voltage Common Mode Range2 TCLK Input Rise/FallTime Maximum Output Frequency
% mV V nS MHz
500 1.2 100 50 25 47.5 45 0.1 -100 -100 -
DC tr, tf t() tsk(O) tsk(B) tPLZ, HZ tPZL, ZH BW
Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Bank-to-Bank Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3dB) Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time
% nS pS pS pS nS nS MHz
/2 Feedback /4 Feedback /8 Feedback Same frequency Multiple frequencies Same frequency Multiple frequencies I/O same VDD
-
tJIT(CC) tJIT(PER) tJIT() tLOCK
pS pS pS mS
Note: 1 AC characteristics apply for parallel output termination of 50 to VTT. Parameters are guaranteed by characterization and are not 100% tested. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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July 2005 rev 0.2
ASM5I9351
Zo = 50 ohm Pulse Generator Z = 50 ohm RT = 50 ohm
Zo = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. LVCMOS_CLK AC Test Reference for VDD = 3.3V / 2.5V
Zo = 50 ohm Differential Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm
VTT VTT
Figure 2. PECL_CLK AC Test Reference for VDD = 3.3V / 2.5V
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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July 2005 rev 0.2
ASM5I9351
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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July 2005 rev 0.2
Package Diagram 32-lead TQFP Package
ASM5I9351
SECTION A-A
Dimensions Symbol
A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e
Inches Min Max
.... 0.0020 0.0374 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0 0.0472 0.0059 0.0413 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7
Millimeters Min Max
... 0.05 0.95 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0 0.8 BASE 1.2 0.15 1.05 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.2 7
0.03937 REF
1.00 REF
0.031 BASE
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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July 2005 rev 0.2
32-lead LQFP Package
ASM5I9351
SECTION A-A
Dimensions Symbol
A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 e a
Inches Min Max
.... 0.0020 0.0531 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0 0.0630 0.0059 0.0571 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7
Millimeters Min Max
... 0.05 1.35 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0 1.6 0.15 1.45 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.20 7
0.03937 REF
1.00 REF
0.031 BASE
0.8 BASE
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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July 2005 rev 0.2
Ordering Information Part Number
ASM5I9351-32-ET ASM5I9351-32-LT ASM5I9351G-32-ET ASM5I9351G-32-LT
ASM5I9351
Marking
ASM5I9351 ASM5I9351 ASM5I9351G ASM5I9351G
Package Type
32-pin TQFP 32-pin LQFP -Tape and Reel 32-pin TQFP, Green 32-pin LQFP -Tape and Reel, Green
Temperature
Industrial Industrial Industrial Industrial
Device Ordering Information
ASM
5I9351
F-32-LT
R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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July 2005 rev 0.2
ASM5I9351
Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com
Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: ASM5I9351 Document Version: 0.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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